RISC-V CPU 设计（4）： RISC-V CPU 设计理论分析与主要模块的实现

package alu

import spinal.core._
import spinal.lib._

class Adder extends Component {
	val io = new Bundle {
		val data1 = in UInt (64 bits)
		val data2 = in UInt (64 bits)
		val subCtr = in Bool()
		val carryOut = out Bool()
		val overflow = out Bool()
		val sign = out Bool()
		val zero = out Bool()
		val adderResult = out UInt (64 bits)
	}
	noIoPrefix()

	val tempResult = UInt(65 bits) //one more bit for carry out

	//CAUTION: Here we need to use +^ as add with carry
	when(io.subCtr) {
		tempResult := io.data1 +^ io.data2 + 1
	} otherwise {
		tempResult := io.data1 +^ io.data2
	}

	when(tempResult === 0) {
		io.zero := True
	} otherwise {
		io.zero := False
	}

	// Only when data1 and data2 are same sign while tempResult has a reversed 'sign bit', overflow happens
	io.overflow := (io.data1.msb & io.data2.msb & ~tempResult(63)) | (~io.data1.msb & ~io.data2.msb & tempResult(63))

	io.sign := tempResult(63)

	io.carryOut := tempResult.msb

	io.adderResult := tempResult(63 downto 0)
}

object AdderVerilog {
	def main(args: Array[String]): Unit =
		SpinalConfig(
			mode = Verilog,
			targetDirectory = "verilog/ALU"
		).generate(new Adder)
}

package alu

import spinal.core._
import spinal.lib._

class Shifter extends Component {
	val io = new Bundle {
		val data = in UInt (64 bits)
		val shamt = in UInt (5 bits)
		val shiftCtr = in UInt (2 bits)
		val shiftResult = out UInt (64 bits)
	}
	noIoPrefix()

	/*
	shiftCtr =
		00 left shift
		01 arithmetical right shift
		10 logical right shift
	 */

	val tempShift = UInt(64 bits)
	//trick: use right shift to get left shift
	tempShift := ((io.shiftCtr === 0) ? io.data.reversed | io.data) |>> io.shamt

	val leftShiftResult = UInt(64 bits)
	leftShiftResult := tempShift.reversed

	val arithRightShiftResult = UInt(64 bits)
	val sraMask = UInt(64 bits)
	sraMask := ~(U"64'hffff_ffff_ffff_ffff" |>> io.shamt)
	arithRightShiftResult := tempShift | (sraMask & U((63 downto 0) -> io.data.msb))

	val logicRightShiftResult = tempShift

	io.shiftResult := io.shiftCtr.mux(
		0 -> leftShiftResult,
		1 -> arithRightShiftResult,
		2 -> logicRightShiftResult,
		default -> U"64'b0"
	)
}

object ShifterVerilog {
	def main(args: Array[String]): Unit = {
		SpinalConfig(
			mode = Verilog,
			targetDirectory = "verilog/ALU"
		).generate(new Shifter)
	}
}

// Logical calculator
val andResult = io.data1 & io.data2
val orResult = io.data1 | io.data2
val xorResult = io.data1 ^ io.data2
val logicResult = logicCtr.mux(
	0 -> andResult,
	1 -> orResult,
	2 -> xorResult,
	default -> S"64'b0"
)

// for SLT & SLTU
val sltLess = adderSign ^ adderOverflow
val sltuLess = ~adderCarryOut
val sltResult = (signCtr ? sltLess | sltuLess) ? S"64'b1" | S"64'b0"

package alu

import spinal.core._
import spinal.lib._

class ALU extends Component {
	val io = new Bundle {
		val aluOp = in UInt (4 bits)
		val data1 = in SInt (64 bits) //from rs1
		val data2 = in SInt (64 bits) //from rs2 or immediate
		val Zero = out Bool()
		val aluResult = out SInt (64 bits)
	}
	noIoPrefix()

	val counter = Reg(UInt(8 bits)) init (0)
	counter := counter + 1
	//get control signal for each module: Adder, Shifter, Logical calculator
	val opCtr = UInt(2 bits)
	switch(io.aluOp) {
		is(U"4'b0000", U"4'b1000") {
			opCtr := 0 //for Adder
		}
		is(U"4'b0001", U"4'b0010") {
			opCtr := 1 //for SLT & SLTU
		}
		is(U"4'b0110", U"4'b0111", U"4'b1001") {
			opCtr := 2 //for Shifter
		}
		is(U"4'b0011", U"4'b0100", U"4'b0101") {
			opCtr := 3 //for logic calculator
		}
		default {
			opCtr := 0
		}
	}
	val signCtr = io.aluOp.mux(
		U"4'b0010" -> False, //no need for adderSign
		default -> True
	)
	val subCtr = io.aluOp.mux(
		U"4'b0001" -> True, //True for subtraction
		U"4'b0010" -> True,
		U"4'b1000" -> True,
		default -> False
	)
	val overflowCtr = io.aluOp.mux(
		U"4'b0010" -> False, //no need for adderOverflow
		default -> True
	)
	val shiftCtr = io.aluOp.mux(
		U"4'b0110" -> U"2'b00", //SLL
		U"4'b0111" -> U"2'b10", //SRL
		U"4'b1001" -> U"2'b01", //SRA
		default -> U"2'b00"
	)
	val logicCtr = io.aluOp.mux(
		U"4'b0011" -> U"2'b00", //AND
		U"4'b0100" -> U"2'b01", //OR
		U"4'b0101" -> U"2'b10", //XOR
		default -> U"2'b00"
	)

	//Adder & SLT
	val adder = new Adder
	adder.io.data1 := io.data1.asUInt
	adder.io.data2 := subCtr ? ~io.data2.asUInt | io.data2.asUInt
	adder.io.subCtr := subCtr
	val adderOverflow = adder.io.overflow
	val adderSign = adder.io.sign
	val adderCarryOut = adder.io.carryOut
	io.Zero := adder.io.zero
	val adderResult = adder.io.adderResult.asSInt
	//for SLT & SLTU
	val sltLess = adderSign ^ adderOverflow
	val sltuLess = ~adderCarryOut
	val sltResult = (signCtr ? sltLess | sltuLess) ? S"64'b1" | S"64'b0"

	//Shifter
	val shifter = new Shifter
	shifter.io.data := io.data1.asUInt
	shifter.io.shamt := io.data2(4 downto 0).asUInt
	shifter.io.shiftCtr := shiftCtr
	val shiftResult = shifter.io.shiftResult.asSInt

	//Logical calculator
	val andResult = io.data1 & io.data2
	val orResult = io.data1 | io.data2
	val xorResult = io.data1 ^ io.data2
	val logicResult = logicCtr.mux(
		0 -> andResult,
		1 -> orResult,
		2 -> xorResult,
		default -> S"64'b0"
	)

	io.aluResult := opCtr.mux(
		0 -> adderResult,
		1 -> sltResult,
		2 -> shiftResult,
		3 -> logicResult
	)
}

object ALUVerilog {
	def main(array: Array[String]): Unit = {
		SpinalConfig(
			mode = Verilog,
			targetDirectory = "verilog/ALU"
		).generate(new ALU)
	}
}

package alu

import spinal.core._
import spinal.core.sim._

object ALUSim {
	def main(args: Array[String]): Unit = {
		SimConfig.withWave.compile(new ALU).doSim { dut =>
			dut.clockDomain.forkStimulus(10)
			SimTimeout(10000)
			dut.clockDomain.waitSampling(10)
			var data1 = 10
			var data2 = 20
			var aluOp = 0
			//ADD SUB
			dut.io.data1 #= data1
			dut.io.data2 #= data2
			dut.io.aluOp #= aluOp

			dut.clockDomain.waitRisingEdge()
			aluOp = 8
			dut.io.aluOp #= aluOp

			//SLT SLTU
			dut.clockDomain.waitRisingEdge()
			aluOp = 1
			dut.io.aluOp #= aluOp

			dut.clockDomain.waitRisingEdge()
			data1 = -10
			dut.io.data1 #= data1

			dut.clockDomain.waitRisingEdge()
			aluOp = 2
			dut.io.aluOp #= aluOp

			dut.clockDomain.waitRisingEdge()
			data1 = 10
			dut.io.data1 #= data1
			dut.io.aluOp #= aluOp

			//AND OR XOR
			dut.clockDomain.waitRisingEdge()
			data1 = 1
			aluOp = 3
			dut.io.data1 #= data1
			dut.io.aluOp #= aluOp

			dut.clockDomain.waitRisingEdge()
			data1 = 65536
			aluOp = 4
			dut.io.data1 #= data1
			dut.io.aluOp #= aluOp

			dut.clockDomain.waitRisingEdge()
			data1 = 10
			data2 = 15
			aluOp = 5
			dut.io.data1 #= data1
			dut.io.data2 #= data2
			dut.io.aluOp #= aluOp

			//SLL SRL SRA
			dut.clockDomain.waitRisingEdge()
			data1 = 128
			data2 = 2
			aluOp = 6
			dut.io.data1 #= data1
			dut.io.data2 #= data2
			dut.io.aluOp #= aluOp

			dut.clockDomain.waitRisingEdge()
			data1 = -2
			aluOp = 7
			dut.io.data1 #= data1
			dut.io.aluOp #= aluOp

			dut.clockDomain.waitRisingEdge()
			aluOp = 9
			dut.io.aluOp #= aluOp

			dut.clockDomain.waitRisingEdge()
			simSuccess()
		}
	}
}

package reg

import spinal.core._
import spinal.lib._

class Register_file extends Component {
	val io = new Bundle {
		val RegWrite = in Bool() // Enable Signal

		val readReg1 = in UInt (5 bits)
		val readReg2 = in UInt (5 bits)
		val writeReg = in UInt (5 bits)

		val writeData = in UInt (64 bits)
		val readData1 = out UInt (64 bits)
		val readData2 = out UInt (64 bits)
	}
	noIoPrefix()
	//Define 32 general registers
	val Regs = Vec(Reg(UInt(64 bits)) init(0), 32)
	//Read Data
	io.readData1 := Regs(io.readReg1)
	io.readData2 := Regs(io.readReg2)
	//Write Data
	when(io.RegWrite) {
		//In fact, here is a trigger. So if you want to pause at anytime, just add "when(~pause signal){do sth..}otherwise{pause..}
		Regs(io.writeReg) := io.writeData
	}
}

object Register_fileVerilog {
	def main(args: Array[String]): Unit = {
		SpinalConfig(
			mode = Verilog,
			targetDirectory = "verilog/Register_file"
		).generate(new Register_file)
	}
}

package reg

import spinal.core.sim._

// Register_file's testbench
object Register_fileSim {
	def main(args: Array[String]): Unit = {
		SimConfig.withWave.compile(new Register_file).doSim { dut =>
			//get clock
			dut.clockDomain.forkStimulus(10)
			SimTimeout(10000)
			dut.clockDomain.waitSampling(10)

			for (i <- 1 to 20) {
				//test write
				dut.io.writeReg #= i + 1
				dut.io.writeData #= i + 1
				if (i < 10) {
					dut.io.RegWrite #= true
				} else {
					dut.io.RegWrite #= false
				}

				//test read
				dut.io.readReg1 #= i
				dut.io.readReg2 #= i - 1

				dut.clockDomain.waitRisingEdge()
				if (i == 7) {
					dut.clockDomain.assertReset()
				} else {
					dut.clockDomain.deassertReset()
				}
			}

			simSuccess()
		}
	}

}